Indian Institute of Information Technology KottayamR01Research Domain · MeitY C2S & 1-TOPS
VLSI, digital/mixed-signal IC, Analog/RFIC, and RTL-to-GDSII ASIC chip design research at I²CS Lab, IIIT Kottayam, Kerala — supported by MeitY Chips to Startup (C2S) and IEEE SSCS Chipathon.
The VLSI, ASIC & Chip Design group at the Intelligent Integrated Circuits and Systems (I²CS) Research Lab, IIIT Kottayam, Kerala, drives indigenous semiconductor design from micro-architecture and Register-Transfer Level (RTL) modeling through physical implementation (GDSII), Design-for-Testability (DfT), and post-silicon validation.
Backed by the Ministry of Electronics and Information Technology (MeitY) Chips to Startup (C2S) Programme, the 1-TOPS (One Tape-Out Per Student) initiative, and the IEEE Solid-State Circuits Society (SSCS) Chipathon, our faculty and student researchers design low-power digital datapaths, custom arithmetic cores, Analog/RF CMOS circuits (LNAs, VCOs, Sub-GHz/5G transceivers), and mixed-signal neural blocks.
Micro-architectural RTL design in Verilog/SystemVerilog, logic synthesis, static timing analysis (STA), floorplanning, placement, clock-tree synthesis, and DRC/LVS signoff.
Low-Noise Amplifiers (LNA), Voltage-Controlled Oscillators (VCO), RF front-end transceivers, and analog perceptron/neuromorphic computing blocks.
Scan-chain insertion, Automatic Test Pattern Generation (ATPG), Built-In Self-Test (BIST), and functional/RTL fault injection for safety-critical silicon.
High-speed POSIT, floating-point, and logarithmic multipliers/adders optimized for power-performance-area (PPA) in deep-submicron nodes.
App No: 202641119737 · Inventors: Joel Dan Philip, Amrut Ayan Gulawani, Shravan Narayan Sunil, Nalesh S, Kala S
Agency: MeitY, Govt of India · Grant: EDA Tool support Lakhs · Duration: 3 Years
Agency: Kerala State Council for Science, Technology and Environment (KSCSTE) · Grant: 0.10 Lakhs
Alan Thomas Paul, Niranjan K S, Adithya Prabhu, Kevin Jose, Kala S, Nalesh S · 40th IEEE International Conference on VLSI Design and 26th International Conference on Embedded Systems (VLSID 2027), Jan 2-16, 2027, Bengaluru, India
Vinayak Bijesh, Ekanath R Das, Kala S · 2026 IEEE 2nd International Conference on Smart Power Control and Renewable Energy (ICSPCRE), NIT Rourkela, India, 2026
G H V S M Soma Sai, P Ramakrishna, Kala S, Nalesh S · In book: VLSI Design for Artificial Intelligence and Machine Learning Applications, Edition: 1 Publisher: Wiley, 2026 DOI: 10.1002/9781394390274.ch15 (Scopus Indexed)
[DOI/Link →]George G.M., Sreekala, K.S., Kala S · Circuits Syst Signal Process (2026). https://doi.org/10.1007/s00034-026-03778-x (SCI Indexed)
[DOI/Link →]Aparna Nair M K, Minu A Pillai, Kala S, Nalesh S · Chips and Intelligence, Edition: 1, Publisher: CRC Press, 2027 Boca Raton, DOI: 10.1201/9781003687924-13 (Scopus)
Adithya Prabhu A, Kevin Jose, Kala S · 19th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2026), Shanghai, China, December 14-17, 2026.
Shravan Narayan Sunil, Joel Dan Philip, Kala S, Nalesh S · 30th International Symposium on VLSI Design and Test (VDAT-2026), Noida, August 20-22, 2026, India
Niranjan K S, Alan Thomas Paul, Prashamol Prakshan, Kala S, Nalesh S · IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2026, July 7-10, 2026, Kolkata, India
Supervisor: Dr. Kala S
