Indian Patent Application 202641119737
Edge-deployed defect detection system, processing circuitry, and method for industrial package sorting
Inventors: Joel Dan Philip, Amrut Ayan Gulawani, Shravan Narayan Sunil, Nalesh S, Kala S
02What we build
Research & Projects
Industry-facing projects and funded research - from FPGA prototypes to products.
Patents Filed
Ongoing Projects
Hardware Accelerator for Sparse Neural Networks
Indo-German Science & Technology Centre (IGSTC), established by DST, Govt of India and the Federal Ministry of Education and Research (BMBF), Government of Germany
Duration: 4 years
Development and Customization of Solutions for Communication, Standards & Protocol, Computing, Logic, AI, ML
Academia-Industry Collaborative Project
Duration: 1 year
Chips to StartUp (C2S) Programme of MeitY, Govt of India
MeitY, Govt of India
Duration: 3 Years
Completed Projects
Design, Modeling and Implementation of Convolutional Neural Networks
Kerala State Council for Science, Technology and Environment (KSCSTE)
Duration: 3 years
An Efficient Sparse Matrix-Vector Multiplier architecture for deep learning
Kerala State Council for Science, Technology and Environment (KSCSTE)
Duration: 6 Months
Faculty Development Programme on "Quantum Computing"
AICTE- ATAL
Duration: 5 Days
Faculty Development Programme on “Internet of Things: Hardware, Software and Applications”
AICTE- ATAL
Duration: 5 Days
Hardware Acceleration of Bandwidth and Energy Efficient Deep Learning Architecture
Technology Development Grant from IIT Palakkad Technology Innovation Hub Foundation (IPTIF) under the National Mission on Interdisciplinary Cyber Physical Systems (NM-ICPS) DST, Govt of India. Technology Development grant no. IPTIF/HRD/DF/020/SEP43
Duration: 4 years
Semiconductor Infrastructure · IIIT Kottayam, Kerala
MeitY Chips to Startup (C2S), EDA Tool Suite & FPGA Prototyping Facilities
Under the Ministry of Electronics and Information Technology (MeitY) Chips to Startup (C2S) consortium, DST NM-ICPS (IIT Palakkad IPTIF), KSCSTE, and IGSTC Indo-German WISER collaborations, the I²CS Research Lab equips researchers and VLSI interns with commercial chip-design flows and modern hardware accelerator boards:
Commercial ASIC & VLSI EDA
Full RTL-to-GDSII digital and custom mixed-signal IC design flows with Synopsys, Cadence, and Siemens EDA toolchains supported under MeitY C2S.
FPGA & RISC-V SoC Platforms
Microchip PolarFire SoC (RISC-V), AMD-Xilinx Zynq UltraScale+ & PYNQ-Z2 boards, and indigenous C-DAC VEGA processor development kits.
International & Industry Partners
Active joint research with Technische Universität Dresden (TU Dresden, Germany), Ruhr University Bochum (Germany), C-DAC, IIT Palakkad IPTIF, and NeST Digital.