Indian Institute of Information Technology KottayamR03Research Domain · Reconfigurable SoCs & RISC-V
FPGA prototyping, Microchip PolarFire SoC, AMD Xilinx Zynq/PYNQ-Z2, and indigenous C-DAC VEGA RISC-V system design at I²CS Research Lab, IIIT Kottayam, Kerala.
The Edge Computing, RISC-V & FPGA System Design group at I²CS Lab, IIIT Kottayam prototypes complete hardware-software systems on state-of-the-art reconfigurable SoCs and indigenous RISC-V processors.
Our student and doctoral teams have won national 1st Place awards at the 39th International Conference on VLSI Design (VLSID 2026) Microchip Design Contest and 10th DVCon India by deploying real-time industrial automation, object detection, and fault-tolerant RISC-V architectures on Microchip PolarFire SoC, AMD Xilinx Zynq/PYNQ-Z2, and C-DAC VEGA platforms.
Deterministic real-time edge AI and industrial defect detection combining hardened 64-bit RISC-V application cores with low-power FPGA fabric.
High-frame-rate YOLO object detection, medical image segmentation, and hardware-accelerated video pipelines with AXI DMA streaming.
Custom ISA extensions, peripheral integration, and embedded sensor fusion on India's indigenous VEGA RISC-V microprocessors.
Ultra-low-power sensor interfaces, piezoelectric energy harvesting power management, and real-time edge inference under tight energy budgets.
App No: 202641119737 · Inventors: Joel Dan Philip, Amrut Ayan Gulawani, Shravan Narayan Sunil, Nalesh S, Kala S
Alan Thomas Paul, Niranjan K S, Adithya Prabhu, Kevin Jose, Kala S, Nalesh S · 40th IEEE International Conference on VLSI Design and 26th International Conference on Embedded Systems (VLSID 2027), Jan 2-16, 2027, Bengaluru, India
Aswin S, Kala S · IEEE International Conference on Smart Electronics and Communication Systems (ISENSE), December 11-12, 2026, Kerala, India
Adithya Prabhu A, Kevin Jose, Kala S · 19th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2026), Shanghai, China, December 14-17, 2026.
Niranjan K S, Alan Thomas Paul, Prashamol Prakshan, Kala S, Nalesh S · IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2026, July 7-10, 2026, Kolkata, India
Aparna Nair M K, Kala S, Asif Muhammed, Nalesh S, Minu A Pillai, Akash Kumar · IETE Journal of Research, 2026 ( SCI Indexed , Impact Factor: 1.5)
Prashamol Prakashan, Nalesh S, Kala S · Quantum Cryptography and Annealing for Securing Industrial IoT, Elsevier, pp 1-11, 2026. ISBN: 978-0-443-38349-6
Remya R, Anand Narayana Gidthuri, Karri Shyam Chandra, Nalesh S, Kala S · IEEE International Conference on Recent Advances in Electronics, Communication, Computing, Automation, and Power (RECCAP 2026), May 2026, IIT Palakkad, Kerala.
Joel Dan Philip, Asif Muhammed, Nalesh S, Kala S · 29th International Symposium on VLSI Design and Test (VDAT-2025), Chandigarh, August 7-9, 2025, India (Best Paper Award)
Supervisor: Dr. Kala S
