R02Research Domain · Custom Silicon & SoC

AI, Deep Learning & Signal Processing Hardware Accelerators

Research on domain-specific hardware accelerators for CNNs, YOLO object detection, FFT/NTT signal processing, and biomedical AI on FPGA and ASIC at I²CS Lab, IIIT Kottayam.

Domain Overview & Research Focus

The Hardware Accelerators group at I²CS Research Lab, IIIT Kottayam focuses on domain-specific architectures that deliver orders-of-magnitude improvements in throughput-per-watt for compute-intensive Artificial Intelligence, Computer Vision, and Digital Signal Processing workloads.

From systolic arrays and reconfigurable Multiply-Accumulate (MAC) engines to high-throughput Fast Fourier Transform (FFT), Number Theoretic Transform (NTT), and Affine Frequency Division Multiplexing (AFDM) processors, our designs bridge algorithmic innovation and silicon efficiency under MeitY C2S, IGSTC WISER, and DST NM-ICPS grants.

Key Research Subtopics & Methodologies

Deep Neural Network & CNN Accelerators

Dataflow-optimized systolic arrays, Winograd/FFT convolution engines, and quantized inference pipelines for real-time vision and edge intelligence.

Next-Gen Wireless & Transform Processors (FFT / AFDM)

High-radix pipelined FFT architectures and Index-Modulated Affine Frequency Division Multiplexing (IM-AFDM) transceivers for 6G and doubly-dispersive channels.

Precision-Scalable & POSIT Compute Engines

Dynamic bit-width arithmetic units and POSIT-based dot-product accelerators that adapt numerical precision to workload sensitivity.

Hardware-Software Co-Design on SoC Platforms

Tightly-coupled AXI/RISC-V custom co-processors off-loading bottlenecks from embedded ARM Cortex and RISC-V host cores.

Selected Publications (47)

View All in Publications →

2026conference

Convolution Architecture and Quantization Analysis for Brain MRI Tumour Image Processing on FPGA

Aswin S, Kala S · IEEE International Conference on Smart Electronics and Communication Systems (ISENSE), December 11-12, 2026, Kerala, India

2026conference

Accelerating CNN on FPGA for Real-time Object Detection in Defense Applications

Adithya Prabhu A, Kevin Jose, Kala S · 19th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2026), Shanghai, China, December 14-17, 2026.

2026conference

Block Floating Point Based Matrix Multiplication Accelerator with Hardware Efficient Exponent Alignment

Shravan Narayan Sunil, Joel Dan Philip, Kala S, Nalesh S · 30th International Symposium on VLSI Design and Test (VDAT-2026), Noida, August 20-22, 2026, India

2026conference

An Optimized Sparse Matrix Storage Format for Neural Network Inference

Aparna Nair M K, Archith P, Minu A Pillai, Nalesh S, Kala S · TENCON 2026 - 2026 IEEE Region 10 Conference (TENCON), Bali, Indonesia, on 10-13 October 2026.

2026journal

Towards Implementing Compression and Decompression Techniques on FPGA for Deep Neural Networks

Aparna Nair M K, Kala S, Asif Muhammed, Nalesh S, Minu A Pillai, Akash Kumar · IETE Journal of Research, 2026 ( SCI Indexed , Impact Factor: 1.5)

2026conference

Hardware Implementation of Activation Functions for Neural Networks on FPGA

Remya R, Anand Narayana Gidthuri, Karri Shyam Chandra, Nalesh S, Kala S · IEEE International Conference on Recent Advances in Electronics, Communication, Computing, Automation, and Power (RECCAP 2026), May 2026, IIT Palakkad, Kerala.

2026conference

Evaluation of Low-Rank Matrix Decomposition Techniques for Data Compression

Remya R, Aswathymol A, Manju Manuel, Kala S · 2nd IEEE International Conference on Advances in Intelligent Computing and Applications (AICAPS), Feb 11-13, 2026, Kerala, India 2025

2025conference

Quantized Residual CNN on FPGA for Real-Time Driver Attention Detection Using hls4ml

Joel Dan Philip, Asif Muhammed, Nalesh S, Kala S · 29th International Symposium on VLSI Design and Test (VDAT-2025), Chandigarh, August 7-9, 2025, India (Best Paper Award)

Dissertations & Theses

All Theses →

phd · 2026Author: Anoop A

Design and Performance Analysis of Index-Modulated Affine Frequency Division Multiplexing Waveforms Using Variational Bayesian and Message Passing Frameworks

Supervisor: Dr. Kala S

phd · 2025Author: Sreelakshmi Raveendran

Analysis and Classification of Disorders of Consciousness Using Machine Learning Methods Based on Scalp EEG

Supervisor: Dr. Kala S

Lab Stories & Updates in this Domain

All Stories →

2026-09-20

Celebrating Undergraduate Research in VLSI & Embedded Systems Congratulations to Shrava…

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AI, Deep Learning & Signal Processing Hardware Accelerators

Domain Overview & Research Focus

Key Research Subtopics & Methodologies

Deep Neural Network & CNN Accelerators

Next-Gen Wireless & Transform Processors (FFT / AFDM)

Precision-Scalable & POSIT Compute Engines

Hardware-Software Co-Design on SoC Platforms

Sponsored Projects & Patents

Hardware Accelerator for Sparse Neural Networks

Design, Modeling and Implementation of Convolutional Neural Networks

An Efficient Sparse Matrix-Vector Multiplier architecture for deep learning

Hardware Acceleration of Bandwidth and Energy Efficient Deep Learning Architecture

Selected Publications (47)

Convolution Architecture and Quantization Analysis for Brain MRI Tumour Image Processing on FPGA

Accelerating CNN on FPGA for Real-time Object Detection in Defense Applications

Block Floating Point Based Matrix Multiplication Accelerator with Hardware Efficient Exponent Alignment

An Optimized Sparse Matrix Storage Format for Neural Network Inference

Towards Implementing Compression and Decompression Techniques on FPGA for Deep Neural Networks

Hardware Implementation of Activation Functions for Neural Networks on FPGA

Evaluation of Low-Rank Matrix Decomposition Techniques for Data Compression

Quantized Residual CNN on FPGA for Real-Time Driver Attention Detection Using hls4ml

Dissertations & Theses

Design and Performance Analysis of Index-Modulated Affine Frequency Division Multiplexing Waveforms Using Variational Bayesian and Message Passing Frameworks

Analysis and Classification of Disorders of Consciousness Using Machine Learning Methods Based on Scalp EEG

Lab Stories & Updates in this Domain

Gurucharan Selected for IEEE SSCS Chipathon Tapeout

Undergraduate Energy Harvesting Research at ASME IMECE 2026

Advancing Semiconductor & VLSI Research at I²CS Research Lab!

Celebrating Undergraduate Research in VLSI & Embedded Systems Congratulations to Shrava…