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R04Research Domain · Low-Power Silicon Arithmetic

Approximate Computing & Energy-Efficient Arithmetic

Research on approximate multipliers, compressors, logarithmic/POSIT arithmetic, and energy-efficient error-resilient VLSI circuits at I²CS Lab, IIIT Kottayam.

Domain Overview & Research Focus

Approximate Computing exploits the inherent error resilience of machine learning, multimedia, image processing, and wireless communication workloads to trade minimal numerical accuracy for substantial reductions in silicon area, critical-path delay, and switching power.

At I²CS Research Lab, IIIT Kottayam, we design novel approximate 4:2 compressors, Booth and Mitchell logarithmic multipliers, speculative adders, and precision-configurable MAC units—validated both in industry CMOS standard-cell libraries (Synopsys/Cadence) and inside end-to-end deep neural network accelerators.

Key Research Subtopics & Methodologies

Approximate Multipliers & High-Order Compressors

Dual-stage and dynamic-truncation approximate multipliers, 4:2 / 5:2 compressors, and partial-product reduction trees with bounded Mean Relative Error Distance (MRED).

Logarithmic, POSIT & Floating-Point Approximation

Hardware-friendly Mitchell logarithmic multipliers and tapered-precision POSIT arithmetic units for energy-constrained neural inference.

Error-Resilient Neural & Image Processing Datapaths

Co-optimizing approximate arithmetic circuits with quantization-aware training so CNN and vision accuracy remains within <0.5% of IEEE-754 baseline.

ASIC Synthesis & PPA Benchmarking

Comprehensive characterization of Power-Delay Product (PDP), Area-Delay Product (ADP), and error metrics across 45nm, 28nm, and 130nm CMOS technology nodes.

Sponsored Projects & Patents

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Completed Project

An Efficient Sparse Matrix-Vector Multiplier architecture for deep learning

Agency: Kerala State Council for Science, Technology and Environment (KSCSTE) · Grant: 0.10 Lakhs

Selected Publications (16)

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2026conference

Hardware Implementation and Evaluation of Efficient Multipliers for Power Electronics Applications

Vinayak Bijesh, Ekanath R Das, Kala S · 2026 IEEE 2nd International Conference on Smart Power Control and Renewable Energy (ICSPCRE), NIT Rourkela, India, 2026

2026conference

Evaluation of Low-Rank Matrix Decomposition Techniques for Data Compression

Remya R, Aswathymol A, Manju Manuel, Kala S · 2nd IEEE International Conference on Advances in Intelligent Computing and Applications (AICAPS), Feb 11-13, 2026, Kerala, India 2025

2025conference

Design and Implementation of Posit Arithmetic-Based FIR Filter on FPGA

Keerthana Menon, Jayakrushna Sahoo, Kala S, Nalesh S · IEEE Region-10 Conference TENCON 2025 (Flagship international conference of IEEE Region-10), October 27-30, 2025, Malaysia

2025conference

PASMA: Bandwidth Efficient, Posit Arithmetic based SpMV Multiplier Architecture on FPGA

Aparna Nair M K, Mahesh M, Minu A Pillai, Nalesh S, Kala S · 5th International Conference on Emerging Electronics and Automation (E2A), December 17-19, 2025, NIT Silchar, India

2025conference

Design of Approximate 6:2 Compressor for Approximate Multiplier

Rachana George, Kondapalli Moulya, Santhos Kumar A, Nalesh S, Kala S · 2025 IEEE Recent Advances in Intelligent Computational Systems (RAICS), Kerala, Nov 20-23, 2025, India.

2025conference

K-means Clustering for Image Segmentation Using Approximate Booth Multiplier

Rachana George, Kala S and Nalesh S · 2nd IEEE International Conference on Trends in Engineering Systems and Technologies (ICTEST), April 3-5, 2025, Kerala, India.

2024journal

Fast approximate booth multiplier for error resilient applications

Rachana George, Rose Mary Kuruvithadam, S Sreeparvathy, S Kala, S Nalesh · International Journal of Signal and Imaging Systems Engineering, pp. 95-108, 2024

2024conference

Approximate Convolution on FPGA Using Multipliers based on 4:2 Compressors

Shivasai Reddy, Rachana George, Nalesh S, Kala S · 2024 IEEE International Conference on Smart Electronics and Communication Systems (ISENSE), December 6-7, 2024, Kerala, India

Dissertations & Theses

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phd · 2025Author: Sreelakshmi Raveendran

Analysis and Classification of Disorders of Consciousness Using Machine Learning Methods Based on Scalp EEG

Supervisor: Dr. Kala S

Lab Stories & Updates in this Domain

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