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I²CS Research Lab · IIIT Kottayam

Dr. Kala S

Head, I²CS Research Lab · Assistant Professor, Department of ECE, IIIT Kottayam

Biography

Biography

Dr. Kala S received her PhD degree from Cochin University of Science And Technology, Kerala, in 2020, her MS (by Research) degree from Center for Nano Science and Engineering (CeNSE), Indian Institute of Science Bangalore in 2013 and BTech in Electronics and Communication Engineering from MG University, Kerala in 2006. Currently she is leading the Intelligent Integrated Circuits and Systems Research Group (I2CS), where she is taking numerous innovative research and development projects for various industries/agencies, leading to products as well as systems. Dr. Kala is a visiting researcher at Chair of Embedded Systems, Faculty of Electrical Engineering and Information Technology at Ruhr University Bochum, Germany, since 2023.

Dr. Kala is the recipient of prestigious WISER Award (Women Involvement in Science and Engineering Research) from Indo-German Science & Technology Centre (IGSTC), established by DST, Govt of India and the Federal Ministry of Education and Research (BMBF), Government of Germany, in the year 2023. Her research, teaching and industry facing activities include Digital System Design, System-On-Chip Design, VLSI and FPGA based system design, Computer Architecture, Intelligent systems for various applications and hardware acceleration of digital signal processing algorithms. She is currently leading research in accelerating deep neural network (DNN) on hardware and approximate computing. She has published research papers in these areas in reputed journals and conferences including TVLSI, ISCAS, VLSID, SOCC, ICM, DTIS, APCCAS and many more. She is the Winner of "Microchip VLSI Design Contest 2025" at 38th IEEE International Conference on VLSI Design (VLSID) held at Bangalore in the year 2025. She has also received 'Honorable Mention Award from Academia' at 36th IEEE International Conference on VLSI Design (VLSID) held at Hyderabad in the year 2023, best paper award at IRTM 2021, and best student research forum award at 33 rd IEEE Int’l Conference on VLSI Design (VLSID) Bangalore, 2020.

Dr. Kala has been keynote speaker in many conferences and has delivered numerous technical talks in her field, in various platforms. She is a reviewer for various international journals including IEEE TVLSI, IEEE TCAD, IEEE TNNLS, IEEE Access, various IET journals, Springer Journals and has been serving in technical review committee of reputed conferences including ISCAS, APCCAS, MWCAS, NEWCAS, VLSID, VDAT, ISED and so on.

She has served as the General Chair of IEEE International Conference on Smart Electronics Systems (ISENSE) organized by IIIT Kottayam in 2025. She has also served as General Co-Chair of IEEE International conference ICITIIT, organized by IIIT Kottayam, in two consecutive years, 2022 and 2023 and has served as session chair in various conferences across globe. She is an IEEE Senior Member and has served as the Treasurer, Women In Engineering (WIE), IEEE Kerala Section for the year 2022. She has served in the Organizing Committee of WIE International Leadership Summit (ILS) 2022, as Finance Co-Chair and Website Chair. She has organized a Special Session titled “Intelligence on Chip” at IEEE 19th India Council International Conference (INDICON) 2022. She has also served in the organizing committee of 19th IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) 2023 as Special Session / Short Paper / Late Breaking Paper (LBR) chair. She has also served as Fellowship Chair for the 28th IEEE VLSI Design and Test (VDAT) Symposium, 2024.

Dr. Kala is currently guiding six students towards their PhD degree; one student has completed PhD under her guidance. She is also guiding several innovative undergraduate projects. One of the UG projects has received Kerala State Innovative Project Award in 2021. She is also serving as supervising guide for several interns from various institutions across the country.

Institutional Profile & Academic Record



Dr. Kala S — Head of I²CS VLSI & Chip Design Research Lab · Assistant Professor (ECE), IIIT Kottayam

Dr. Kala S

Assistant Professor
Indian Institute of Information Technology Kottayam
Valavoor P.O, Pala
Kottayam - 686635, Kerala, India.
Email: kala at iiitkottayam dot ac.in
Hello at: 00 91 04822202167
Website: https://i2cs.iiitkottayam.ac.in/
Projects / Grants :
  • Project in the broad area of "Hardware Accelerators for Deep Learning", funded by Indo-German Science & Technology Centre (IGSTC), established by the Department of Science & Technology (DST), Government of India and the Federal Ministry of Education and Research (BMBF), Government of Germany. Duration - 4 years; 2023, Sanctioned Amount: 39 Lakhs, (Role: Principal Investigator), Collaborator: Prof. (Dr.) Akash Kumar (Chaired Professor of Processor Design), Technische Universitat Dresden (TUD), Germany
  • Chips to StartUp (C2S) Programme of MeitY, Govt. of India for EDA Tool support for three years. (Role: Chief Investigator)
  • Technology Development Grant from IIT Palakkad Technology Innovation Hub Foundation (IPTIF) under the National Mission on Interdisciplinary Cyber Physical Systems (NM-ICPS) DST, Govt of India. Duration : 2021-2026 (5 years), Sanctioned Amount: 18.14 Lakhs, Grant no. IPTIF/HRD/DF/020/SEP43 (Role: Principal Investigator)
  • Kerala State Council for Science, Technology and Environment (KSCSTE) Student Project entitled "An Efficient Sparse Matrix-Vector Multiplier architecture for deep learning", Letter no. 00188 /SPS 65/ 2021 / KSCSTE, 2021, Sanctioned Amount: Rs. 0.10 Lakh (Role: Principal Investigator)
  • AICTE- ATAL sponsored 5-days Faculty Development Programme on "Quantum Computing", 12-16 July, 2021, Sanctioned amount: 0.93 Lakhs (Role: FDP Coordinator)
  • Academia-Industry collaborative project, "Development of On Board Diagnostic System for Connected Cars / Two Wheelers", Duration: One year, Amount: 5 Lakhs (Role: Principal Investigator)
  • Kerala State Council for Science, Technology and Environment (KSCSTE) project entitled “Design, Modeling and Implementation of Convolutional Neural Networks”, with a total outlay of Rs.9,70,800/-. Council (P) Order No 742/2018/KSCSTE, dated 05/12/2018. (Role: Principal Investigator)
  • AICTE ATAL sponsored Five-days Faculty Development Programme on “Internet of Things: Hardware, Software and Applications”, December 2020, Sanctioned amount Rs. 0.93 Lakhs (Role: FDP Coordinator)
Honours and Achievements :
  • Winner, VLSI Design Contest (Microchip) – First Prize in Design Contest at VLSID 2026 (Winner for SECOND consecutive year) at 39th IEEE International Conference on VLSI Design and 25th International Conference on Embedded Systems, (VLSID), Pune, January 3-7, 2026, organized by VLSI Society of India. Project title: "AI-Based Defect Detection and Smart Rejection for Industrial Automation on PolarFire SoC".
  • "Winner of Microchip VLSI Design Contest 2025" : First Prize for VLSI Design Contest (Microchip) at 38th IEEE International Conference on VLSI Design and 24th Int'l Conference on Embedded Systems (VLSID 2025), Jan 4-8, 2025, Bangalore, for the project titled "AI Driven Retail Automation using PolarFire SoC".
  • Women Involvement in Science and Engineering Research (WISER) Award (2023), by Indo-German Science & Technology Centre (IGSTC), established by DST, Govt of India and the Federal Ministry of Education and Research (BMBF), Government of Germany.
  • Best Paper Award: 29th International Symposium on VLSI Design and Test (VDAT), Chandigarh, August 7-9, 2025
  • Winner, DVCON Design Contest – First Place in Design and Verification Design Contest at Design and Verification Conference (DVCon), Bangalore, September 2025
  • Best Paper Award at 11th IEEE International Conference on Smart Computing and Communications (ICSCC) 2025, technically sponsored by IEEE Kerala Section, July 2025.
  • Visiting Researcher, Faculty of Electrical Engineering and Information Technology, Embedded Systems, Ruhr University Bochum (RUB), Germany
  • Member, ICC Team, India Semiconductor Mission, MeitY, Govt. of India: ICC Faculty member in Strategic Research Area, System Design and Architecture, ISM
  • "Women in Space leadership Program (WiSLP)", organized by DST, Govt. of India and British Council, under UK-India Education and Research Initiative (UKIERI) Scheme, held at IACS Kolkata, January 2025
  • Invited WISER awardee, for meeting with the German Federal Minister of Education and Research Ms. Bettina Stark-Watzinger, at New Delhi on October 25, 2024
  • "Honorary Mention Award for Academia" at 36th IEEE International Conference on VLSI Design (VLSID 2023), Jan 8-12, 2023, Hyderabad
  • Best Paper Award in International Conference on Interdisciplinary Research in Technology and Management (IRTM), Kolkata, 26-28 Feb, 2021
  • Best Student Research Forum (Runner Up), in 33rd IEEE International Conference on VLSI Design & 19th International Conference on Embedded Systems (VLSID), Bengaluru, 4-8 January, 2020
  • Kerala State Council for Science, Technology and Environment (KSCSTE) Woman Scientist Research Fellow (2018-2019)
  • CSIR Foreign Travel Grant, for attending and presenting a paper at 32 nd IEEE System-On-Chip Conference (SOCC) 2019, September 3-6, 2019, Singapore
  • VLSID 2020 Fellowship, for presentation at Student Research Forum at 33 rd IEEE International Conference on VLSI Design & 19 th International Conference on Embedded Systems (VLSID’20), Bengaluru, 4-8 January 2020
  • VLSID 2019 Fellowship, for attending and presenting a paper at 32 nd IEEE International Conference on VLSI Design & 18 th International Conference on Embedded Systems (VLSID’19) 2019, New Delhi, NCR, 5-9 Jan 2019
  • MHRD Fellowship, for pursuing Master of Science (Engineering) By Research, at Indian Institute of Science (IISc) Bangalore (2010-2013)
  • GARP Fund from Indian Institute of Science (IISc) Bangalore, for attending and presenting a paper at IEEE International Symposium on Circuits And Systems (ISCAS) 2013, Beijing,China, May 2013.
  • Kerala State Council for Science Technology and Environment (KSCSTE) TECHFEST, 'State Level Contest for Innovative Engineering Projects', Bronze Prize for the project titled "HRIDITA - A Healthcare Partner", BTech Project Student: Mr. Rahul Barnwal, November 2021 (Role: Project Guide)
Education :
  • Ph.D, Cochin University of Science And Technology, Thesis titled: "Accelerating Two Dimensional FFT and Convolutional Neural Networks on FPGA", 2020.
  • Master of Science (Engineering) By Research, Centre for Nano Science and Engineering (CeNSE), Indian Institute of Science (IISc) Bengaluru, Thesis titled : “ASIC Implementation of High Throughput, Low Latency, Memory Optimized FFT Processor”, 2013.
  • M.Tech., VLSI Design, Anna University, Tamil Nadu, 2007-2009
  • B.Tech., Electronics and Communication and Engineering, MG University, Kerala, 2002-2006
Patent Filed:
  1. Title of Invention: Edge-deployed defect detection system, processing circuitry, and method for industrial package sorting
    Inventors: Joel Dan Philip, Amrut Ayan Gulawani, Shravan Narayan Sunil, Nalesh S, Kala S
    Indian Patent Application Number: 202641119737
Publications
For details of all publications,Please visit googleScholar or DBLP
Journals
  1. Kala S., Babita R Jose, Jimson Mathew, Nalesh S., “High Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture,” in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 27, No. 12, pp 2816-2828, December 2019., DOI: 10.1109/TVLSI.2019.2941250
  2. Aparna Nair M K, Kala S, Asif Muhammed, Nalesh S, Minu A Pillai, Akash Kumar, “Towards Implementing Compression and Decompression Techniques on FPGA for Deep Neural Networks”, IETE Journal of Research, 2026. https://doi.org/10.1080/03772063.2026.2647371
  3. Sweety Kunjachan, Anjuru Muni Santhosh, C Selvi, A Santhos Kumar, Kala S, “Towards Adulteration Detection in Medicinal Leaves Using an Effective Feature Extractor”, IETE Technical Review, pp 1-12, 2026. https://doi.org/10.1080/02564602.2026.2621331
  4. Anoop A, Christo K Thomas, Kala S, J.V. Bibal Benifa, Walid Saad, “Multi-mode Index Modulation based on Affine Frequency Division Multiplexing”, Physical Communication, Elsevier, 2026, 103059, ISSN 1874-4907, https://doi.org/10.1016/j.phycom.2026.103059.
  5. Noble G, Nalesh S, Kala S, Akash Kumar, Salim Ullah “MdCSR: A Memory-Efficient Sparse Matrix Compression Format”, IEEE Embedded System Letters (ESL), 2025, DOI: 10.1109/LES.2025.3598189
  6. Kala S., Jimson Mathew, Babita R Jose, Nalesh S., “Radix-4 3 based Two Dimensional FFT Architecture with Efficient Data Reordering Scheme”, IET Computers and Digital Techniques, 2019, Vol. 13 Iss. 2, pp.78-86, DOI:10.1049/iet-cdt.2018.5075.
  7. Kala S., Nalesh S., S K Nandy, Ranjani Narayan; “Scalable and Energy Efficient, Dynamically Reconfigurable FFT Architecture", Journal of Low Power Electronics (JOLPE), Vol. 11, No. 3, pp. 426-435(10), September 2015. American Scientific Publishers. DOI:https://doi.org/10.1166/jolpe.2015.1390
  8. Kala S, Nalesh S, "Efficient CNN Accelerator on FPGA", IETE Journal of Research, 2020
  9. Muneeb M, Nalesh S, Kala S., “A Physically Unclonable Function Architecture with Multiple Responses on FPGA”, in International Journal of Embedded Systems, 2023, Vol. 16, No. 1, pp.67–74.
  10. Raveendran S, Kenchaiah R, Kumar S, Sahoo J, Farsana MK, Chowdary Mundlamuri R, Bansal S, Binu VS, Ramakrishnan AG, Ramakrishnan S and Kala S, “Variational mode decomposition-based EEG analysis for the classification of disorders of consciousness”, Frontiers in Neuroscience, 2024, Front. Neurosci. 18:1340528. doi: 10.3389/fnins.2024.1340528
  11. Noble G, Nalesh S, Kala S, Akash Kumar, “Configurable Sparse Matrix - Matrix Multiplication Accelerator on FPGA: A Systematic Design Space Exploration Approach with Quantization Effects”, Alexandria Engineering Journal, Elsevier, 2024
  12. Anoop A, Christo K Thomas, Kala S, “Enhanced Spatial Modulation based Orthogonal Time Frequency Space System”, IEICE Transactions on Communications, 2024
  13. Anoop A., Christo K Thomas, Kala S., J.V. Bibal Benifa, Walid Saad, "Dual-mode Index Modulation based on Affine Frequency Division Multiplexing", Physical Communication, Elsevier, Volume 70, 2025, 102628, ISSN 1874-4907, https://doi.org/10.1016/j.phycom.2025.102628.
  14. Sreelakshmi Raveendran, Kala S, A G Ramakrishnan, R Kenchiah, Jayakrushna Sahoo, Santhos Kumar, Farsana M K, Ravindranadh Mundlamuri, Sonia Bansal, BINU V S, Subasree R, “Functional Connectivity in EEG: A Multiclass Classification Approach for Disorders of Consciousness”, Frontiers in Neuroscience, Volume 19, 2025, DOI=10.3389/fnins.2025.1550581, ISSN=1662-453X
  15. Rachana George, Rose Mary Kuruvithadam, S Sreeparvathy, S Kala, S Nalesh, “Fast approximate booth multiplier for error resilient applications”, International Journal of Signal and Imaging Systems Engineering, pp. 95-108, 2024
  16. Kavitha Pillai, Nalesh S, Ramesh Chintala, Kala S, ”Enhancing Autonomous Wheelchair Mobility: A Holistic Method for Dynamic Route Planning”, International Journal of Systems, Control and Communications, 2025.
  17. George, G.M., Sreekala, K.S., Kala, S. A Novel Power-Efficient Foot-Driven Domino Logic Circuit with Self-adaptive Keeper for VLSI Design. Springer Circuits Syst Signal Process (2026). https://doi.org/10.1007/s00034-026-03778-x
International Conferences
  1. Alan Thomas Paul, Niranjan K S, Adithya Prabhu, Kevin Jose, Kala S, Nalesh S, “Measuring Interface Observability for In-Field Fault Detection in RISC-V Cores”, 40th IEEE International Conference on VLSI Design and 26th International Conference on Embedded Systems (VLSID 2027), Jan 2-16, 2027, Bengaluru, India
  2. Adithya Prabhu A, Kevin Jose, Kala S, “Accelerating CNN on FPGA for Real-time Object Detection in Defense Applications”, 19th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2026), Shanghai, China, December 14-17, 2026.
  3. Shravan Narayan Sunil, Joel Dan Philip, Kala S, Nalesh S, “Block Floating Point Based Matrix Multiplication Accelerator with Hardware Efficient Exponent Alignment”, 30th International Symposium on VLSI Design and Test (VDAT-2026), Noida, August 20-22, 2026, India
  4. Aparna Nair M K, Archith P, Minu A Pillai, Nalesh S, Kala S, “An Optimized Sparse Matrix Storage Format for Neural Network Inference”, TENCON 2026 - 2026 IEEE Region 10 Conference (TENCON), Bali, Indonesia, on 10–13 October 2026.
  5. Anoop A, Christo K Thomas, J V Bibal Benifa, Kala S, “A GAMP Detector for Dual-Mode Index Modulated AFDM in High-Mobility Channels”, TENCON 2026 - 2026 IEEE Region 10 Conference (TENCON), Bali, Indonesia, on 10–13 October 2026.
  6. Alan Thomas Paul, Niranjan K S, Adithya Prabhu, Kevin Jose, Kala S, Nalesh S, “Measuring Interface Observability for In-Field Fault Detection in RISC-V Cores”, 40th IEEE International Conference on VLSI Design and 26th International Conference on Embedded Systems (VLSID 2027), Jan 2-16, 2027, Bengaluru, India
  7. Niranjan K S, Alan Thomas Paul, Prashamol Prakshan, Kala S, Nalesh S, "Design and Hamiltonian Characterization of 4-Qubit Flip-Chip Transmon-Based Quantum Random Number Generator", IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2026, July 7-10, 2026, Kolkata, India
  8. Keerthana Menon, Goutam Mali, Nalesh S, Babita Jajodia, Kala S, "Hybrid FSR-based Pseudo-Random Number Generator on FPGA for Encrypting Biometrics", IEEE 37th International Conference on Microelectronics (ICM) 2025, December 14-17, 2025, Cairo, Egypt
  9. Anoop A, Christo K Thomas, J V Bibal Benifa, Kala S, "Variational Bayesian Detection for Quantized AFDM Systems", 2026 IEEE Wireless Communications and Networking Conference (WCNC), 13-16 April 2026, Malaysia
  10. Anoop A, Christo K Thomas, J V Bibal Benifa, Kala S, "Low-Complexity VAMP Detector for Affine Frequency Division Multiplexing Systems", 2026 IEEE Wireless Communications and Networking Conference (WCNC), 13-16 April 2026, Malaysia
  11. Anoop A, Christo K Thomas, J V Bibal Benifa, Kala S, "Variational Bayesian Spectrum Sensing over AFDM Waveforms in Doubly-Dispersive Channels", IEEE International Symposium on Dynamic Spectrum Access Networks (DySPAN), 11-14 May 2026, Washington, DC, USA
  12. Anoop A, Christo K Thomas, J V Bibal Benifa, Kala S, "Multi-Path Bayesian Inference for Symbol Detection in Affine Frequency Division Multiplexing", 32nd National Conference on Communications (NCC) 2026, February 26 - March 1, 2026, Hyderabad, India
  13. Aparna Nair M K, Mahesh M, Minu A Pillai, Nalesh S, Kala S, "PASMA: Bandwidth Efficient, Posit Arithmetic based SpMV Multiplier Architecture on FPGA", 5th International Conference on Emerging Electronics and Automation (E2A), December 17-19, 2025, NIT Silchar, India
  14. Joel Dan Philip, Asif Muhammed, Nalesh S, Kala S, “Quantized Residual CNN on FPGA for Real-Time Driver Attention Detection Using hls4ml”, 29th International Symposium on VLSI Design and Test (VDAT-2025), Chandigarh, August 7-9, 2025, India(Best Paper Award)
  15. Kala S, Anand Mukhopadhyay, "Accelerating System Design: HDL Code Generation and Verification Techniques", (Tutorial), 29th International Symposium on VLSI Design and Test (VDAT-2025), Chandigarh, August 7-9, 2025, India
  16. Keerthana Menon, Jayakrushna Sahoo, Kala S, Nalesh S, “Design and Implementation of Posit Arithmetic-Based FIR Filter on FPGA”, IEEE Region-10 Conference TENCON 2025 (Flagship International Conference of IEEE Region-10), October 27-30, 2025, Malaysia
  17. Remya R, Amritha Anujan, Nalesh S, Libin T T, Shibu M R, Premjith A V, Krishnakumar Rao, Kala S, “RISC-V SoC Compatible ViT Accelerator for Malware Detection”, 11th IEEE International Symposium on Smart Electronic Systems (IEEE – iSES), Jaipur, India, 15-17 December 2025.
  18. Kondapalli Moulya, Rachana George, Santhos Kumar A, Nalesh S, Kala S, “'Design of Approximate 6:2 Compressor for Approximate Multiplier”, 2025 IEEE Recent Advances in Intelligent Computational Systems (RAICS), Kerala, Nov 20-23, 2025, Kerala, India.
  19. Rachana George, Kala S and Nalesh S, “K-means Clustering for Image Segmentation Using Approximate Booth Multiplier”, 2nd International Conference on Trends in Engineering Systems and Technologies (ICTEST), April 3-5, 2025, Kerala, India.
  20. Sreelakshmi Raveendran, Kala S, A G Ramakrishnan, R Kenchiah, Jayakrushna Sahoo, Santhos Kumar, Farsana M K, Ravindranadh Chowdary Mundlamuri, Sonia Bansal, Binu V S and Subasree R, “Network Dynamics in Disorders of Consciousness: A Graph Theoretical Perspective”, 6th IEEE International Conference on Control, Communication and Computing (ICCC 2025), May 23- 25, 2025, Kerala, India
  21. Anoop A, Christo K Thomas, J.V. Bibal Benifa and Kala S, “Affine Frequency Division Multiplexing With Generalized Index Modulation”, 2025 11th International Conference on Smart Computing and Communications (ICSCC), July 2025, Kerala, India(Best Paper Award)
  22. Aparna Nair M. K., Nandhu Sam, Minu A Pillai, Nalesh S, Kala S, “Implementation and Analysis of Sparse DNN on GPU”, 10th IEEE International Symposium on Smart Electronic Systems (iSES 2024), December 16-18, 2024, New Delhi, India
  23. Aparna Nair M. K., B. Sravani, Minu A Pillai, Nalesh S, Kala S, “Neural Network using Double MAC based Block Matrix Multiplication on FPGA”, IEEE 21st India Council International Conference INDICON 2024 (Flagship annual international conference of IEEE India Council), December 19-21, 2024, IIT Kharagpur, India.
  24. Rohith George Ninan, Kala S, “FPGA-based Acceleration of Homomorphic Convolution with Plaintext Kernels”, 14th International Conference on Security, Privacy and Applied Cryptographic Engineering (SPACE), Kerala, December 14-17, 2024, India.
  25. Sweety Kunjachan, Anjuru Muni Santhosh, Kala S, “A Novel CNN Architecture for Herb Classification”, IEEE Region-10 Conference TENCON 2024 (Flagship international conference of IEEE Region-10), December 1-4, 2024, Singapore.
  26. Aparna Nair M K, B. Sravani, Minu A Pillai, Nalesh S, Kala S, “Implementation of Neural Network on Hardware”, 28th International Symposium on VLSI Design and Test (VDAT-2024), Tamil Nadu, September 1-3, 2024, India (Poster).
  27. Sreelakshmi R, Kala S, R Kenchiah, Jayakrushna Sahoo, Farsana M K, Ravindranadh Chowdary Mundlamuri, Sonia Bansal, Binu V S, A G Ramakrishnan, and Subasree R: "Machine learning-based consciousness assessment in disorders of consciousness patients", 2024 International Conference on Brain-Computer Interface & Healthcare Technologies (iConBCI-HT Conference), Kerala, December 19-20, 2024, India.
  28. Prashamol Prakashan, Harsh Gupta, S Nalesh, Kala S, “A Configurable AES Implementation on FPGA for Secure 5G Systems” 2024 IEEE Recent Advances in Intelligent Computational Systems (RAICS), Kerala, May 2024, India.
  29. Noble G, Nalesh S, Kala S, “Bit-Flip Attack Detection in Sparse Matrix Computations on FPGA”, in 19th IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), 19-22 November 2023, Hyderabad, India (Flagship conference of IEEE CAS Society)
  30. Rahul Barnwal, Noble G, Rajesh Kedia, Kala S, Nalesh S, “Leveraging PolarFire SoC for Heartbeat Classification using Convolutional Neural Networks”, in 19th IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS) Co-located with PRIMEAsia, 19-22 November 2023, Hyderabad, India
  31. Abhinav K, Rachana George, Nalesh S, Kala S, “Approximate CNN on FPGA Using Toom-Cook Multiplier”, in 9th IEEE International Symposium on Smart Electronic Systems (iSES 2023), Dec 18-20, 2023, Ahmedabad, India
  32. Vishnu Bajjuri, Nalesh S, Kala S, "A Novel Adiabatic PUF for Portable Devices", in 36th IEEE International Conference on VLSI Design and 22nd International Conference on Embedded Systems (VLSID 2023), Jan 8-12, 2023, Hyderabad, India (VLSID 2023 UDT Award - Honorary Mention Award for Academia)
  33. Noble G, Nalesh S, Kala S, "MOSCON: Modified Outer Product based Sparse Matrix-Matrix Multiplication Accelerator with Configurable Tiles", in 36th IEEE International Conference on VLSI Design and 22nd International Conference on Embedded Systems (VLSID 2023), Jan 7-12, 2023, Hyderabad, India.
  34. Vishnu Bajjuri, Nalesh S, Sree Ranjani Rajendran, Kala S, "Adiabatic Physical Unclonable Function Using Cross-Coupled Pair", in 8th IEEE International Symposium on Smart Electronic Systems (iSES 2022), Dec 19-21, India.
  35. Noble G, Nalesh S, Kala S, "Accelerators for Sparse Matrix-Matrix Multiplication: A Review", in IEEE 19th India Council International Conference (INDICON 2022), Nov 24-26, 2022, Kerala, India.
  36. Rahul Barnwal, Rishab Srivastava, Vimalathithan R, Kala S, "Advanced Driver Assistance System for Autonomous Vehicles Using Deep Neural Network", in 2022 IEEE 10th Region 10 Humanitarian Technology Conference (R10-HTC), Sept 18-18, 2022, Hyderabad, India.
  37. Mahesh M, Nalesh S, Kala S, "Bandwidth-Efficient Sparse Matrix Multiplier Architecture for Deep Neural Networks on FPGA", in 34th IEEE International System-On-Chip Conference (SOCC), Las Vegas, NV, USA, September 2021.
  38. Mahesh M, Nalesh S, Kala S, "Hardware Acceleration of SpMV Multiplier for Deep Learning", in 25th International Symposium on VLSI Design and Test (VDAT-2021), Surat, India, September 2021.
  39. Shivakrishna G and Kala S, "Sewage Monitoring System for Smart City Using Internet of Things", in International Conference on Interdisciplinary Research in Technology and Management (IRTM), Kolkata, 26-28 Feb, 2021. (Best Paper Award)
  40. Tumun Shaily, Kala S., "Bacterial Image Classification using Convolutional Neural Networks", 17th IEEE India Council International Conference (INDICON), December 2020.
  41. Kala S., Babita R Jose, Jimson Mathew, Nalesh S., “Efficient hardware acceleration of convolutional neural networks,” 32nd IEEE International System-On-Chip Conference (SOCC) 2019, Singapore, Sept 3-6, 2019.
  42. Kala S., Jimson Mathew, Babita R Jose, Nalesh S., “UniWiG: Unified Winograd- GEMM Architecture for Accelerating CNN on FPGAs”, 32nd International Conference on VLSI Design and 18th International Conference on Embedded systems (VLSID) 2019, New Delhi, Jan 5-9, 2019 (Under Top 12 papers in VLSID’19)
  43. Kala S., Babita R Jose, Jimson Mathew, Nalesh S., “Accelerating Convolutional Neural Networks on FPGA”, 33rd International Conference on VLSI Design and 19th International Conference on Embedded systems (VLSID) 2020, Bengaluru, Jan 4-8, 2020 (Student Research Forum)
  44. Kala S., Debdeep Paul, Babita R Jose, Jimson Mathew, Nalesh S., “Performance Analysis of Convolutional Neural Network Models,” 9th International Conference on Advances in Computing and Communications (ICACC) 2019, Kochi, Nov 6-8, 2019.
  45. Kala S., Debdeep Paul, Babita R Jose, Nalesh S., “Design space exploration of convolution algorithms to accelerate CNNs on FPGA”, IEEE 8th International Symposium on Embedded computing & system Design (ISED), Kochi, Dec 13-15, 2018.
  46. Kala S., Debdeep Paul, Babita R Jose, Jimson Mathew, “Accelerating Convolutional Neural Networks on FPGA using Fast Fourier Transform”, 22nd International Symposium on VLSI Design and Test (VDAT-2018), Tamil Nadu, June 28-30, 2018.
  47. Kala S., Nalesh S., Babita R Jose, Jimson Mathew, Marco Ottavi, “Two dimensional FFT architecture based on radix-4 3 algorithm with efficient output reordering”, IEEE 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS), Taormina, Italy, April 9-12, 2018
  48. Kala S., Nalesh S., Arka Maity, S K Nandy, Ranjani Narayan; “High Throughput, Low Latency, Memory Optimized 64K Point FFT Architecture using Novel Radix-4 Butterfly Unit” in IEEE International Symposium on Circuits And Systems (ISCAS) Beijing, China, May 2013.
  49. Kala S., Nalesh S., S K Nandy, Ranjani Narayan; “Design of a Low Power 64 Point FFT Architecture for WLAN Applications”, in 25th IEEE International Conference on Microelectronics (ICM), Beirut, Lebanon, December 2013.
  50. Kala S., Nalesh S., S K Nandy, Ranjani Narayan; “Energy Efficient, Scalable and Dynamically Reconfigurable FFT Architecture for OFDM Systems”, in IEEE International Symposium on Electronic Design (ISED), Karnataka, December, 2014.
Book Chapters
  1. Aparna Nair M K, Minu A Pillai, Kala S, Nalesh S, “Hardware ecosystem for AI”, Chips and Intelligence, Edition: 1, Publisher: CRC Press, 2027, Boca Raton, DOI: 10.1201/9781003687924-13 (Scopus)
  2. Prashamol Prakashan, Nalesh S, Kala S, “Efficient Quantum Cryptography in Industrial IoT for Optimized Performance Energy and Resource Utilization”, Quantum Cryptography and Annealing for Securing Industrial IoT, Elsevier, pp 1-11, 2026. ISBN: 978-0-443-38349-6
  3. Kala S., Nalesh S., Babita R Jose, Jimson Mathew; “Image Reconstruction using Novel Fourier Transform”, Advances in Soft Computing and Machine Learning for Image Processing, Springer 2018, pp. 699-718, https://doi.org/10.1007/978-3-319-63754-9_31
  4. Kala S, Nalesh S., “Security and Challenges in IoT Enabled Systems”, System Assurances, Elsevier, pp 437-445, Jan 2022
  5. R Remya, Nalesh S, Kala S., “Edge AI – A Promising Technology”, Nanodevices for Integrated Circuit Design, Wiley October 2023, pp 211-222, https://doi.org/10.1002/9781394186396.ch11
  6. Rahul Barnwal, Aman Kumar, Kala S, Sree Ranjani Rajendran, “The Intelligent Universe: AI’s Role in Astronomy”, Scrivener Publishing, Wiley, 2025.
  7. G H V S M Soma Sai, P Ramakrishna, Kala S, Nalesh S, “In Memory Computing Using Memristors” VLSI for Artificial Intelligence and Machine Learning Applications” published by Wiley and Scrivener, 2025
Professional Activities
  1. Chair, Design Contest-Tape-Out at 40th International Conference on VLSI Design (VLSID) 2027, Bangalore, Jan 2027, Organized by VLSI Society of India & IEEE
  2. Co-ordinator, IEEE Computer Society TTTC India (Test Technology Training Council) sponsored Workshop on VLSI Test, IIIT Kottayam, India during 30.01.2026 - 01.02.2026
  3. Mentor for Digital Design Hackathon under C2S Programme (Invited through ChipIN, CDAC - MeitY), Chips to Startup Program, MeitY, Govt. of India, held at Bangalore 2025, India, February 16- 20, 2025, Organized by CDAC Bangalore and MeitY, Govt of India
  4. Member of Judging Panel, PhD Forum, 38th IEEE International Conference on VLSI Design and 24th International Conference on Embedded Systems, (VLSID), Bangalore, January 04-08, 2025
  5. Academic Council Member, Kerala Technological University (KTU) Nominee, Federal Institute of Science And Technology (FISAT) Kerala (Autonomous) (2026-2029)
  6. Member, Board of Studies (BoS), UKF College of Engineering and Technology, Kerala (Autonomous) (2025-2028)
  7. Member, Board of Studies (BoS), Chennai Institute of Technology, Chennai, Tamil Nadu (Autonomous) (2026-2029)
  8. General Co-Chair, IEEE International Conference on Smart Electronics and Communication Systems (iSENSE) 2026, Organized by IIIT Kottayam, technically sponsored by IEEE Kerala Section, December 11-12, 2026, India
  9. Session Chair, 29th International Symposium on VLSI Design and Test (VDAT) 2025, Organized by VLSI Society of India and IEEE Circuits And Systems Society, August 7-9, 2025, Chandigarh, India
  10. General Chair, IEEE International Conference on Smart Electronics and Communication Systems (iSENSE) 2024, Organized by IIIT Kottayam, technically sponsored by IEEE Kerala Section, December 6-7, 2024, India
  11. Organizing Committee (Fellowship Chair), International Symposium on VLSI Design and Test (VDAT) 2024, Organized by VLSI Society of India and IEEE Circuits And Systems Society, September 1-3, 2024 India
  12. Technical Program Committee (Track Chair – VLSI and Embedded Systems), 5th IEEE Int’l conference on Recent Advances in Intelligent Computational Systems (RAICS), Kerala, Organized by IEEE Kerala Section, May 16-18, 2024, India
  13. Coordinator, IEEE CAS Society Kerala Section sponsored 5-Day FDP on “Recent trends in VLSI and MEMS”, Organized by IIIT Kottayam, May 3-7, 2024.
  14. Organizer, IEEE CAS Society Kerala Section, sponsored 2-Day Hands-On Workshop on “DIR-V VEGA Processor and Ecosystem”, organized jointly with C-DAC Thiruvananthapuram and IIIT Kottayam, February 2-3, 2024
  15. Organizing Committee Member (Chair, Special Session / Late Breaking Research Paper), 19th Edition IEEE Asia-Pacific Conference on Circuits And Systems (APCCAS), 19-22 November 2023, Hyderabad, India (Flagship Conference of IEEE CAS Society) (APCCAS being hosted for the first time in INDIA ! )
  16. Coordinator, IEEE CAS Society Kerala Section sponsored 5-Day Workshop and FDP on “Integrated Circuits and Systems for AI”, 8-12 May 2023, IIIT Kottayam
  17. Chair, PhD Forum, 28th International Conference on Advanced Computing and Communications (ADCOM), ACCS India, Dec 8-10, 2023, Kochi, India.
  18. General Co-Chair, 4th IEEE International Conference on Innovative Trends In Information Technology (ICITIIT), Organized by Indian Institute of Information Technology Kottayam and technically co-sponsored by IEEE Kerala Section, 11–12 Feb 2023.
  19. Organizer of a Special Session titled "Intelligence on Chip", at IEEE 19th India Council International Conference (INDICON 2022), Nov 24-26, 2022, Kerala, India.
  20. Session Chair for the track "Electronic Systems and Smart Technologies" in IEEE 19th India Council International Conference (INDICON 2022), Nov 24-26, 2022, Kerala, India.
  21. Treasurer, Women In Engineering (WIE), IEEE Kerala Section, 2022
  22. Chair, Website Committee, IEEE WIE International Leadership Summit (ILS), Trivandrum, Kerala, Organized by IEEE Kerala Section, 29-30 July 2022.
  23. Co-Chair, Finance Committee, IEEE WIE International Leadership Summit (ILS), Trivandrum, Kerala, Organized by IEEE Kerala Section, 29-30 July 2022.
  24. Delivered Keynote address/Invited talks at conferences and Invited talks/Seminars at various institutions across India
  25. Organizing Co-Chair, 3rd IEEE International Conference on Innovative Trends In Information Technology (ICITIIT), Organized by Indian Institute of Information Technology Kottayam and technically co-sponsored by IEEE Kerala Section, 12–13 Feb 2022
  26. Doctoral Committee Member (as Subject Expert) for PhD scholars, at Amrita Vishwa Vidyapeetham, India , June 2021 – Till date
  27. Member, Judging Panel, ‘Final Year Project Award’, IEEE Kerala Section, Organized by Strategic Initiatives for Academic Engagement (SIAE) and Student Activities Committee of IEEE Kerala Section, in association with Genskill, 15.07.2021
  28. Session Chair, 8th IEEE International Conference on Smart Computing and Communication (ICSCC), 1-3 July 2021, Organized by Muthoot Institute of Science and Technology, Kerala
  29. IEEE Student Branch Counselor, IIIT Kottayam, 18.05.2020–Till Date
  30. Advisor, IEEE CAS Society Student Chapter, IIIT Kottayam
  31. PhD Thesis Examiner, REVA University, Bangalore
PhD Guidance
  • Sreelakshmi R (August 2019–August 2025) [First PhD from Dept of ECE, IIIT Kottayam]
    Status – Completed (Thesis Defended on Aug 28, 2025)
  • Anoop A (January 2022–September 2026) [First Integrated PhD (MS+PhD) from IIIT Kottayam]
    Status – Completed (Thesis Defended on 23rd Sept 2026)
  • Sweety Kunjachan (August 2022–Ongoing)
  • Aparna Nair K (August 2023–Ongoing)
  • Prashamol Prakasan (August 2022–Ongoing)
  • Remya R (August 2022–Ongoing)
  • Nitha M Biju (August 2025–Ongoing)
Membership in Professional Body
  • Member, VLSI Society of India
  • Member, ACM
  • IEEE Member (Served as Executive Committee Member (EXECOM), IEEE Sensor’s Council, Bangalore Section, during 2014-2015)
  • Associate Member, Institution of Engineers (India)
  • Senior Member, IEEE
  • Senior Member IEEE and Member IEEE CAS Society
Major Conferences Attended and Presented Papers
  1. IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2026, July 7-10, 2026, Kolkata, India
  2. 39th IEEE International Conference on VLSI Design and 25th International Conference on Embedded Systems, (VLSID) Pune, India, January 3-7, 2026
  3. CASES, CODES+ISSS: International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, collocated with Embedded Systems Week (ESWEEK), Taipei, Taiwan, Sept 28 – Oct 3, 2025
  4. 29th IEEE International Symposium on VLSI Design and Test (VDAT), Chandigarh, India, 7-9 August 2025
  5. 38th IEEE International Conference on VLSI Design and 24th International Conference on Embedded Systems, (VLSID) Bangalore, India, January 4-8, 2025
  6. SEMICON India 2024, Greater Noida, September 11-13, 2024
  7. 28th IEEE International Symposium on VLSI Design and Test (VDAT), Tamil Nadu, India, September 1-3, 2024
  8. 37th IEEE International Conference on VLSI Design and 23rd International Conference on Embedded Systems, (VLSID) Kolkata, India, January 6-10, 2024
  9. 19th IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), Hyderabad, India, November 2023
  10. 36th IEEE International Conference on VLSI Design and 22nd International Conference on Embedded Systems, (VLSID) Hyderabad, India, January 2023 (Recipient of Honorable Mention Award from Academia)
  11. 34th IEEE International System-On-Chip Conference (SOCC), Las Vegas, USA (Virtual Conference), September 2021
  12. 25th IEEE International Symposium on VLSI Design and Test (VDAT), Surat, India (Virtual Conference) September 2021
  13. 33rd IEEE International Conference on VLSI Design and 19th International Conference on Embedded Systems, (VLSID) Bangalore, India, January 2020 (Best Student Research Forum - Runner Up)
  14. 32nd IEEE International System-On-Chip Conference (SOCC), Singapore, September 2019
  15. 32nd IEEE International Conference on VLSI Design and 18th International Conference on Embedded Systems, (VLSID) New Delhi, India January 2019 (Under Top 12 papers, among 80+ papers presented)
  16. 8th IEEE International Symposium on Embedded System Design (ISED), Kerala, India, December 2018
  17. 22nd International Symposium on VLSI Design And Test (VDAT), Tamil Nadu, India, April 2018
  18. 4th IEEE International Symposium on Embedded System Design (ISED), Karnataka, India, December 2014
  19. IEEE International Symposium on Circuits And Systems (ISCAS), Beijing, China, May 2013 (Flagship Conference of IEEE CAS Society)
Reviewer:
Peer Reviewer of Journals and Conferences
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
  • IEEE Asia Pacific Conference on Circuit And Systems (APCCAS)
  • IEEE NEWCAS
  • 36th VLSI Design Conference (VLSID)
  • Int'l Symposium on Smart Electronic Systems (iSES)
  • IEEE Transactions on VLSI Systems
  • IEEE Transactions on Neural Networks and Learning Systems
  • IET Signal Processing
  • IEEE Access
  • Journal of Supercomputing, Springer
  • IEEE Int’l Symposium on Embedded System Design (ISED), India, (various editions from 2010 onwards)
  • 16th IEEE Asia Pacific Conference on Circuit And Systems (APCCAS), Vietnam, 2021
  • 8th IEEE International Conference on Smart Computing and Communications (ICSCC), Kochi Kerala, 2021
  • International Conference on Data Science Engineering, IIT Patna, 2019
  • IEEE International Symposium on Circuits And Systems (ISCAS), Florence, Italy, 2018
  • Symposium on Intelligent Systems Technologies and Applications (ISTA), India, (various editions from 2018 onwards)
  • International Conference on Eco-friendly Computing, India, 2017
  • International Conference on Advances in Computing and Communications (ICACC, Kochi), 2016
Research Interests :
  • Reconfigurable Architectures
  • SoC Design Methodologies
  • FPGA and ASIC
  • VLSI and Embedded systems
  • Deep Learning Architectures
  • EDA and CAD tools
  • Secure Processor Architectures
  • Edge Computing
  • Hardware Security
  • Quantum Circuits and Quantum Chips
Internship/Summer projects
  • If you are interested in pursuing higher studies or internship in the area of VLSI and Reconfigurable computing, then you can always write to me at kala@iiitkottayam.ac.in