Congratulations to MAHESH M - IIITK (3rd year BTech) on the acceptance of our paper at the 34th IEEE International System-On-Chip Conference (SOCC), Las Vegas, NV, 2021 Paper details: Mahesh M, Nalesh S , Kala S, "Bandwidth-Efficient Sparse Matrix Multiplier Architecture for Deep Neural Networks on FPGA" https://lnkd.in/dUqjUFfn
Explore I²CS VLSI Research, Projects & Internships at IIIT Kottayam
Discover our MeitY Chip-to-Startup (C2S), IGSTC Indo-German, and DST funded projects, IEEE/Springer publications, Ph.D. dissertations, and VLSI/FPGA internship tracks.

