Attended the “VLSI EDA Tools for FPGA & ASIC Design” workshop organised by the Departme…

Attended the “VLSI EDA Tools for FPGA & ASIC Design” workshop organised by the Department of Electronics, CUSAT from December 4th to 8th. Had an amazing hands-on experience with the Zybo Z7 FPGA board. Witnessing the RTL modules I had written previously come to life was rewarding. One highlight was exporting a design written in High-Level C into a Verilog IP using Vitis HLS, and seamlessly integrating it using the IP integrator of Xilinx Vivado to run on the FPGA. A heartfelt thank you to Dr. Nalesh S for granting me access to the resources of the VLSI lab at CUSAT. Also, I extend my gratitude to Dr. Kala S for for her invaluable mentorship and guidance. Looking forward to applying these skills in future projects!