1-TOPS (One Tape-Out Per Student) kicked off!

🚀 Excited to begin our 1-TOPS journey, an ambitious hands-on program aimed at enabling undergraduate students to achieve a complete silicon tape-out. As part of this initiative, students will work end-to-end on the design and tape-out of a RISC-V processor, gaining exposure to the entire VLSI design flow-from RTL design and functional verification to synthesis, physical design, timing closure, DRC/LVS, and sign-off methodologies. With the guidance of our Industry coach, Prasan Shanbhag , students will dive deep into industry-standard tools, PDKs, and best practices, bridging the critical gap between academic learning and real-world semiconductor design. This program emphasizes not just theory, but practical design trade-offs, constraints, and tape-out readiness, which are essential for VLSI engineers. A commendable initiative by the VLSI Society of India (VSI) , under the leadership of Dr. Satya Gupta and Ms. Chitra Hariharan , 1-TOPS is a significant step toward nurturing silicon-ready talent in the country. Looking forward to an intense and rewarding journey of learning, debugging, and building silicon-ready designs. Shravan Narayan Sunil Joel Dan Philip Johan Mathew John Shaun Sebastian Kevin Jose Seejo Amritha Anujan Dr. Kala S Indian Institute of Information Technology Kottayam